Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.2.3.2. Instruction and Data Caches

This section first describes the similar characteristics of the instruction and data cache memories, and then describes the differences.

Both the instruction and data cache addresses are divided into fields based on whether or not an MMU is present in your system.

Table 60.  Cache Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tag line
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line offset
Table 61.  Cache Virtual Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
  line
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line offset
Table 62.  Cache Physical Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tag  
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  offset

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