Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.5.1. MPU Region Read and Write Operations

MPU region read and write operations are operations that access MPU region attributes through the mpubase and mpuacc control registers. The mpubase.BASE, mpuacc.MASK, mpuacc.LIMIT, mpuacc.MT, and mpuacc.PERM fields comprise the MPU region attributes.

MPU region read operations retrieve the current values for the attributes of a region. Each MPU region read operation consists of the following actions:

  • Execute a wrctl instruction to the mpubase register with the mpubase.INDEX and mpubase.D fields set to identify the MPU region.
  • Execute a wrctl instruction to the mpuacc register with the mpuacc.RD field set to one and the mpuacc.WR field cleared to zero. This action loads the mpubase and mpuacc register values.
  • Execute a rdctl instruction to the mpubase register to read the loaded the mpubase register value.
  • Execute a rdctl instruction to the mpuacc register to read the loaded the mpuacc register value.

The MPU region read operation retrieves mpubase.BASE, mpuacc.MASK or mpuacc.LIMIT, mpuacc.MT, and mpuacc.PERM values for the MPU region.

Note: Values for the mpubase register are not actually retrieved until the wrctl instruction to the mpuacc register is performed.

MPU region write operations set new values for the attributes of a region. Each MPU region write operation consists of the following actions:

  • Execute a wrctl instruction to the mpubase register with the mpubase.INDEX and mpubase.D fields set to identify the MPU region.
  • Execute a wrctl instruction to the mpuacc register with the mpuacc.WR field set to one and the mpuacc.RD field cleared to zero.

The MPU region write operation sets the values for mpubase.BASE, mpuacc.MASK or mpuacc.LIMIT, mpuacc.MT, and mpuacc.PERM as the new attributes for the MPU region.

Normally, a wrctl instruction flushes the pipeline to guarantee that any side effects of writing control registers take effect immediately after the wrctl instruction completes execution. However, wrctl instructions to the mpubase and mpuacc control registers do not automatically flush the pipeline. Instead, system software is responsible for flushing the pipeline as needed (either by using a flushp instruction or a wrctl instruction to a register that does flush the pipeline). Because a context switch typically requires reprogramming the MPU regions for the new thread, flushing the pipeline on each wrctl instruction would create unnecessary overhead.

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