2.7.5. Hardware Triggers
Hardware trigger conditions are based on either the instruction or data bus. Trigger conditions on the same bus can be logically ANDed, enabling the JTAG debug module to trigger, for example, only on write cycles to a specific address.
|Specific address||Data, Instruction||Trigger when the bus accesses a specific address.|
|Specific data value||Data||Trigger when a specific data value appears on the bus.|
|Read cycle||Data||Trigger on a read bus cycle.|
|Write cycle||Data||Trigger on a write bus cycle.|
|Armed||Data, Instruction||Trigger only after an armed trigger event. Refer to the Armed Triggers section.|
|Range||Data||Trigger on a range of address values, data values, or both. Refer to the Triggering on Ranges of Values section.|
When a trigger condition occurs during processor execution, the JTAG debug module triggers an action, such as halting execution, or starting trace capture. The table below lists the trigger actions supported by the Nios II JTAG debug module.
|Break||Halt execution and transfer control to the JTAG debug module.|
|External trigger||Assert a trigger signal output. This trigger output can be used, for example, to trigger an external logic analyzer.|
|Trace on||Turn on trace collection.|
|Trace off||Turn off trace collection.|
|Trace sample||Store one sample of the bus to trace buffer.|
|Arm||Enable an armed trigger.|
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