Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.7.5. Hardware Triggers

Hardware triggers activate a debug action based on conditions on the instruction or data bus during real-time program execution. Triggers can do more than halt processor execution. For example, a trigger can be used to enable trace data collection during real-time processor execution.

Hardware trigger conditions are based on either the instruction or data bus. Trigger conditions on the same bus can be logically ANDed, enabling the JTAG debug module to trigger, for example, only on write cycles to a specific address.

Table 3.  Trigger Conditions
Condition Bus Description
Specific address Data, Instruction Trigger when the bus accesses a specific address.
Specific data value Data Trigger when a specific data value appears on the bus.
Read cycle Data Trigger on a read bus cycle.
Write cycle Data Trigger on a write bus cycle.
Armed Data, Instruction Trigger only after an armed trigger event. Refer to the Armed Triggers section.
Range Data Trigger on a range of address values, data values, or both. Refer to the Triggering on Ranges of Values section.

When a trigger condition occurs during processor execution, the JTAG debug module triggers an action, such as halting execution, or starting trace capture. The table below lists the trigger actions supported by the Nios II JTAG debug module.

Table 4.  Trigger Actions
Action Description
Break Halt execution and transfer control to the JTAG debug module.
External trigger Assert a trigger signal output. This trigger output can be used, for example, to trigger an external logic analyzer.
Trace on Turn on trace collection.
Trace off Turn off trace collection.
Trace sample  Store one sample of the bus to trace buffer.
Arm Enable an armed trigger.
Note: For the Trace sample triger action, only conditions on the data bus can trigger this action.

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