Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Document Table of Contents

8.5.50. initda

Instruction initialize data cache address

Initializes the data cache line currently caching address rA + σ(IMM16)

Assembler Syntax

initda IMM16(rA)


initda -100(r6)


If the Nios® II processor implements a direct mapped data cache, initda clears the data cache line without checking for (or writing) a dirty data cache line that is mapped to the specified address back to memory. Unlike initd, initda clears the cache line only when the addressed data is currently cached. This process comprises the following steps:

  • Compute the effective address specified by the sum of rA and the signed 16-bit immediate value.
  • Identify the data cache line associated with the computed effective address. Each data cache effective address comprises a tag field and a line field. When identifying the line, initda uses both the tag field and the line field.
  • Compare the cache line tag with the effective address to determine if the addressed data is currently cached. If the tag fields do not match, the effective address is not currently cached, so the instruction does nothing.
  • Skip checking if the data cache line is dirty. Because initd skips the dirty cache line check, data that has been modified by the processor, but not yet written to memory is lost.
  • Clear the valid bit for the line.

    If the Nios® II processor core does not have a data cache, the initda instruction performs no operation.


Use initda to skip writing dirty lines back to memory and to flush the cache line only if the addressed memory location is currently in the cache. By contrast, refer to “flushd flush data cache line”, “flushda flush data cache address”, and “initd initialize data cache line” on page 8–55 for other cache-clearing options. Use initda with caution because it does not write back dirty data.

For more information on the Nios II data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook.


Supervisor-only data address

Fast TLB miss (data)

Double TLB miss (data)

MPU region violation (data)

Unimplemented instruction

Instruction Type


Instruction Fields

A = Register index of operand rA

IMM16 = 16-bit signed immediate value

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x13

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