Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents MMU TLB RAM

  1. Use a WRCTL instruction to set ECCINJ.TLB to INJS or INJD.
  2. Use a WRCTL instruction to write a TLB entry. The ECC error is injected at this time and any associated uTLB entry can be flushed.
  3. Use a RDCTL instruction to ensure the value of ECCINJ.TLB is NOINJ.
  4. Perform an instruction/data access to cause the hardware to read the TLB entry (copied into uTLB) and the ECC decoder should detect the ECC error at this time. Alternatively, initiate a software read of the TLB (by writing TLBMISC.RD to 1).
  5. If a software read was initiated, the TLBMISC.EE field should be set to 1 on any instruction after the WRCTL that triggered the software read.
  6. If a hardware read was initiated, the ECC error should be triggered on the first instruction after the hardware read.