Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.9.1. Data Transfer Instructions

The Nios® II architecture is a load-store architecture. Load and store instructions handle all data movement between registers, memory, and peripherals. Memories and peripherals share a common address space. Some Nios® II processor cores use memory caching as well as write buffering to improve memory bandwidth. The architecture provides instructions for both cached and uncached accesses.
Table 44.  Wide Data Transfer Instructions
Instruction Description
ldw
stw
The ldw and stw instructions load and store 32-bit data words from/to memory. The effective address is the sum of a register's contents and a signed immediate value contained in the instruction. Memory transfers can be cached or buffered to improve program performance. This caching and buffering might cause memory cycles to occur out of order, and caching might suppress some cycles entirely.

Data transfers for I/O peripherals should use ldwio and stwio.

ldwio
stwio
ldwio and stwio instructions load and store 32-bit data words from/to peripherals without caching and buffering. Access cycles for ldwio and stwio instructions are guaranteed to occur in instruction order and are never suppressed.
Table 45.  Narrow Data Transfer Instructions
Instruction Description
ldb
ldbu
stb 
ldh
ldhu
sth
ldb, ldbu, ldh and ldhu load a byte or half-word from memory to a register. ldb and ldh sign-extend the value to 32 bits, and ldbu and ldhu zero-extend the value to 32 bits.

stb and sth store byte and half-word values, respectively.

Memory accesses can be cached or buffered to improve performance. To transfer data to I/O peripherals, use the io versions of the instructions, described in the following table cell.

ldbio
ldbuio
stbio
ldhio
ldhuio
sthio
These operations load/store byte and half-word data from/to peripherals without caching or buffering.

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