Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.11.2. Nested Exceptions with an External Interrupt Controller

With an EIC, handling of nested interrupts is more sophisticated than with the internal interrupt controller. Handling of noninterrupt exceptions, however, is the same.

When individual external interrupts have dedicated shadow register sets, the Nios® II processor supports fast interrupt handling with no overhead for saving register contents. To take full advantage of fast interrupt handling, system software must set up certain conditions. With the following conditions satisfied, ISRs need not save and restore register contents on entry and exit:

  • Automatic nested interrupts are enabled.
  • Each interrupt is assigned to a dedicated shadow register set.
  • All interrupts with the same RIL are assigned to dedicated shadow register sets.
  • Multiple interrupts with different RILs can be assigned to a single shadow register set. However, with multiple register sets, you must not allow the RILs assigned to one shadow register set to overlap the RILs assigned to another register set.

    The following tables demonstrate the validity of register set assignments when preemption within a register set is enabled.

Table 42.  Example of Illegal RIL Assignment
RIL Register Set 1 Register Set 2
1 IRQ0  
2 IRQ1  
3   IRQ2
4 IRQ3  
5   IRQ4
6   IRQ5
7   IRQ6
Table 43.  Example of Legal RIL Assignment
RIL Register Set 1 Register Set 2
1 IRQ0  
2 IRQ1  
3 IRQ3  
4   IRQ2
5   IRQ4
6   IRQ5
7   IRQ6
Note: Noninterrupt exception handlers must always save and restore the register contents, because they run in the normal register set.

Multiple interrupts can share a register set, with some loss of performance. There are two techniques for sharing register sets:

  • Set status.RSIE to 0. When an ISR is running in a given register set, the processor does not take any maskable interrupt assigned to the same register set. Such interrupts must wait for the running ISR to complete, regardless of their interrupt level.
Note: This technique can result in a priority inversion.
  • Ensure that each ISR saves and restores registers on entry and exit, and set status.RSIE to 1 after registers are saved. When an ISR is running in a given register set, the processor takes an interrupt in the same register set if it has a higher interrupt level.

The Nios® II processor disables interrupts when taking a maskable interrupt (nonmaskable interrupts always disable maskable interrupts). Individual ISRs can re-enable nested interrupts by setting status.PIE to 1, as described in the Nested "Exceptions with Internal Interrupt Controller" section of this chapter.

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