Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.8. The pteaddr Register

The pteaddr register contains the virtual address of the operating system’s page table and is only available in systems with an MMU. The pteaddr register layout accelerates fast TLB miss exception handling.
Table 17.  pteaddr Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTBASE  
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPN Rsvd
Table 18.  pteaddr Control Register Field Descriptions
Field Description Access Reset Available
PTBASE PTBASE is the base virtual address of the page table. Read/Write 0 Only with MMU
VPN VPN is the virtual page number. VPN can be set by both hardware and software. Read/Write 0 Only with MMU

Software writes to the PTBASE field when switching processes. Hardware never writes to the PTBASE field.

Software writes to the VPN field when writing a TLB entry. Hardware writes to the VPN field on a fast TLB miss exception, a TLB permission violation exception, or on a TLB read operation. The VPN field is not written on any exceptions taken when an exception is already active, that is, when status.EH is already one.

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