Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.3.2.1. Multiply and Divide Performance

The Nios II/s core provides the following hardware multiplier options:

  • DSP Block—Includes DSP block multipliers available on the target device. This option is available only on Intel FPGAs that have DSP Blocks.
  • Embedded Multipliers—Includes dedicated embedded multipliers available on the target device. This option is available only on Intel FPGAs that have embedded multipliers.
  • Logic Elements—Includes hardware multipliers built from logic element (LE) resources.
  • None—Does not include multiply hardware. In this case, multiply operations are emulated in software.

The Nios II/s core also provides a hardware divide option that includes LE-based divide circuitry in the ALU.

Including an ALU option improves the performance of one or more arithmetic instructions.

Note: The performance of the embedded multipliers differ, depending on the target FPGA family.
Table 68.  Hardware Multiply and Divide Details for the Nios II/s Core
ALU Option Hardware Details Cycles per instruction Supported Instructions
No hardware multiply or divide Multiply and divide instructions generate an exception None
LE-based multiplier ALU includes 32 x 4-bit multiplier 11 mul, muli
Embedded multiplier on Stratix III families ALU includes 32 x 32-bit multiplier 3 mul, muli, mulxss, mulxsu, mulxuu
Embedded multiplier on Cyclone III families ALU includes 32 x 16-bit multiplier 5 mul, muli
Hardware divide ALU includes multicycle divide circuit 4 – 66 div, divu

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