Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

5.2.1. Overview

The Nios II/f core:
  • Has separate optional instruction and data caches
  • Provides optional MMU to support operating systems that require an MMU
  • Provides optional MPU to support operating systems and runtime environments that desire memory protection but do not need virtual memory management
  • Can access up to 4 GB of external address space when bit31 is not enabled
  • Supports optional external interrupt controller (EIC) interface to provide customizable interrupt prioritization
  • Supports optional shadow register sets to improve interrupt latency
  • Supports optional tightly-coupled memory for instructions and data
  • Employs a 6-stage pipeline to achieve maximum DMIPS/MHz
  • Performs dynamic or static branch prediction
  • Provides optional hardware multiply, divide, and shift options to improve arithmetic performance
  • Supports the addition of custom instructions
  • Optional ECC support for internal RAM blocks (data cache, data cache victim buffer RAM, instruction and data tightly-coupled memories, instruction cache, MMU TLB, and register file)
  • Supports the JTAG debug module
  • Supports optional JTAG debug module enhancements, including hardware breakpoints and real-time trace

The following sections discuss the noteworthy details of the Nios II/f core implementation. This document does not discuss low-level design issues or implementation details that do not affect Nios® II hardware or software designers.