Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

4.2.2. Exception Vector

Parameters in this section select the memory module where the general exception vector (exception address) resides, and the location of the general exception vector. The general exception vector cannot be configured until your system memory components are in place.

The Exception vector memory list, which includes all memory modules mastered by the Nios® II processor, selects the exception vector memory module. In a typical system, select a low-latency memory module for the exception code.

Exception vector offset specifies the location of the exception vector relative to the memory module’s base address. Platform Designer calculates the physical address of the exception vector when you modify the memory module, the offset, or the memory module’s base address. In Platform Designer, Exception vector displays the read-only, calculated address.. The address is always a physical address, even when an MMU is present.

Note: Platform Designer provides an Absolute option, which allows you to specify an absolute address in Exception vector offset. Use an absolute address when the memory storing the exception handler is located outside of the processor system and subsystems of the processor system.

For information about exceptions, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

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