Usually the instruction and data master ports share a single memory that contains both instructions and data. While the processor core has separate instruction and data buses, the overall Nios® II processor system might present a single, shared instruction/data bus to the outside world. The outside view of the Nios® II processor system depends on the memory and peripherals in the system and the structure of the system interconnect fabric.
The data and instruction master ports never cause a gridlock condition in which one port starves the other. For highest performance, assign the data master port higher arbitration priority on any memory that is shared by both instruction and data master ports.