Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.3.1. Memory Regions

The MPU contains up to 32 instruction regions and 32 data regions. Each region is defined by the following attributes:
  • Base address
  • Region type
  • Region index
  • Region size or upper address limit
  • Access permissions
  • Default cacheability (data regions only)

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