Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.5.1. Processing a Break

A break causes the processor to take the following steps:
  1. Stores the contents of the status register to bstatus.
  2. Clears status.PIE to zero, disabling maskable interrupts.
Note: Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be taken while processing a break exception.
  1. Writes the address of the instruction following the break to the ba register (r30) in the normal register set.
  2. Clears status.U to zero, forcing the processor into supervisor mode, when the system contains an MMU or MPU.
  3. Sets status.EH to one, indicating the processor is handling an exception, when the system contains an MMU.
  4. Copies status.CRS to status.PRS and then sets status.CRS to 0.
  5. Transfers execution to the break handler, stored at the break vector specified in the Nios® II Processor parameter editor.
Note: All noninterrupt exception handlers, including the break handler, must run in the normal register set.

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