Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.1. Terminology

Intel FPGA Nios® II Gen 2 and Nios® II documentation uses the following terminology to discuss exception processing:
  • Exception—a transfer of control away from a program’s normal flow of execution, caused by an event, either internal or external to the processor, which requires immediate attention.
  • Interrupt—an exception caused by an explicit request signal from an external device; also: hardware interrupt.
  • Interrupt controller—hardware that interfaces the processor to interrupt request signals from external devices.
  • Internal interrupt controller—the nonvectored interrupt controller that is integral to the Nios® II processor. The internal interrupt controller is available in all revisions of the Nios® II processor.
  • Vectored interrupt controller (VIC)—an Intel-provided external interrupt controller.
  • Exception (interrupt) latency—The time elapsed between the event that causes the exception (assertion of an interrupt request) and the execution of the first instruction at the handler address.
  • Exception (interrupt) response time—The time elapsed between the event that causes the exception (assertion of an interrupt request) and the execution of non-overhead exception code, that is, specific to the exception type (device).
  • Global interrupts—All maskable exceptions on the Nios® II processor, including internal interrupts and maskable external interrupts, but not including nonmaskable interrupts.
  • Worst-case latency—The value of the exception (interrupt) latency, assuming the maximum disabled time or maximum masked time, and assuming that the exception (interrupt) occurs at the beginning of the masked/disabled time.
  • Maximum disabled time—The maximum amount of continuous time that the system spends with maskable interrupts disabled.
  • Maximum masked time—The maximum amount of continuous time that the system spends with a single interrupt masked.
  • Shadow register set—a complete alternate set of Nios II general-purpose registers, which can be used to maintain a separate runtime context for an ISR.

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