Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

4.7.7. Exception Checking

The Exception Checking settings provide the following options:

Misaligned memory access—Misaligned memory access detection is only available for the Nios® II/f core. When Misaligned memory access is on, the processor checks for misaligned memory accesses.

Note: When your system contains an MMU or MPU, the processor automatically generates misaligned memory access exceptions. Therefore, the Misaligned memory access check box is always disabled when Include MMU or Include MPU on the Core Nios® II tab are on.

There are two misaligned memory address exceptions:

  • Misaligned data address—Data addresses of load and store instructions are checked for misalignment. A data address is considered misaligned if the byte address is not a multiple of the data width of the load or store instruction (4 bytes for word, 2 bytes for half-word). Byte load and store instructions are always aligned so never generate a misaligned data address exception.
  • Misaligned destination address—Destination instruction addresses of br, callr, jmp, ret, eret, and bret instructions are checked for misalignment. A destination instruction address is considered misaligned if the target byte address of the instruction is not a multiple of four.

Your exception handler can use this code to quickly determine the proper action to take, rather than have to determine the cause of an exception through instruction decoding. Additionally, some exceptions also store the instruction or data address associated with the exception in the badaddr register.

For further descriptions of exceptions, exception handling, and control registers, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

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