Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

8.5.87. stb / stbio l

Instruction store byte to memory or I/O periphera
Operation

Mem8[rA + σ(IMM16)] ←  rB7..0

Assembler Syntax

stb rB, byte_offset(rA)

stbio rB, byte_offset(rA)

Example

stb r6, 100(r5)

Description

Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. Stores the low byte of rB to the memory byte specified by the effective address.

Usage

In processors with a data cache, this instruction may not generate an Avalon® -MM bus cycle to noncache data memory immediately. Use the stbio instruction for peripheral I/O. In processors with a data cache, stbio bypasses the cache and is guaranteed to generate an Avalon® -MM data transfer. In processors without a data cache, stbio acts like stb.

Exceptions

Supervisor-only data address

Misaligned data address

TLB permission violation (write)

Fast TLB miss (data)

Double TLB miss (data)

MPU region violation (data)

Instruction Type

I

Instruction Fields

A = Register index of operand rA

B = Register index of operand rB

IMM16 = 16-bit signed immediate value

Table 105.  stb
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x05
Table 106.  stbio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x25

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