Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6. Memory and I/O Organization

This section explains hardware implementation details of the Nios II memory and I/O organization. The discussion covers both general concepts true of all Nios® II processor systems, as well as features that might change from system to system.

The flexible nature of the Nios II memory and I/O organization are the most notable difference between Nios® II processor systems and traditional microcontrollers. Because Nios® II processor systems are configurable, the memories and peripherals vary from system to system. As a result, the memory and I/O organization varies from system to system.

A Nios II core uses one or more of the following to provide memory and I/O access:

  • Instruction master port—An Avalon® ® Memory-Mapped ( Avalon® -MM) master port that connects to instruction memory via system interconnect fabric
  • Instruction cache—Fast cache memory internal to the Nios II core
  • Data master port—An Avalon® -MM master port that connects to data memory and peripherals via system interconnect fabric
  • Data cache—Fast cache memory internal to the Nios II core
  • Tightly-coupled instruction or data memory port—Interface to fast on-chip memory outside the Nios II core

The Nios II architecture handles the hardware details for the programmer, so programmers can develop Nios II applications without specific knowledge of the hardware implementation.

For details that affect programming issues, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

Figure 3. Nios II Memory and I/O Organization

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