Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
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3.4.2.4. The ienable Register

The ienable register controls the handling of internal hardware interrupts. Each bit of the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A value of one in bit n means that the corresponding irqn interrupt is enabled; a bit value of zero means that the corresponding interrupt is disabled. Refer to the Exception Processing section for more information.
Note: When the internal interrupt controller is not implemented, the value of the ienable register is always 0.