Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6.1. Instruction and Data Buses

The Nios II architecture supports separate instruction and data buses, classifying it as a Harvard architecture. Both the instruction and data buses are implemented as Avalon® -MM master ports that adhere to the Avalon® -MM interface specification. The data master port connects to both memory and peripheral components, while the instruction master port connects only to memory components.

Note: The Nios® II instruction and data masters have a combined address map. The memory model is arranged so that instructions and data are in the same address space.

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