2.6.1. Instruction and Data Buses
The Nios II architecture supports separate instruction and data buses, classifying it as a Harvard architecture. Both the instruction and data buses are implemented as Avalon® -MM master ports that adhere to the Avalon® -MM interface specification. The data master port connects to both memory and peripheral components, while the instruction master port connects only to memory components.
Did you find the information on this page useful?