Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents Data Cache Victim Line Buffer RAM

  1. Use a LOAD instruction to load a data cache line.
  2. Use a WRCTL instruction to set ECCINJ.DCWB field to INJS or INJD (as desired).
  3. Use a STORE instruction to an address in the data cache line.
  4. Use a RDCTL instruction to ensure the values of the field written by the WRCTL to ECCINJ is NOINJ. Before the RDCTL, use a FLUSHP instruction to avoid the RAW hazard on ECCINJ.
  5. Either use a LOAD instruction from the same address or trigger a writeback of the dirty line (e.g. FLUSHDA instruction)
  6. The ECC error should be triggered on the LOAD instruction unless it is only detected during the writeback of a dirty line. In the writeback of a dirty line case, the ECC error is triggered an undefined number of instructions later.