Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

8.5. Instruction Set Reference

The following pages list all Nios II instruction mnemonics in alphabetical order.
Table 94.  Notation Conventions
Notation Meaning
X ← Y X is written with Y
PC ← X The program counter (PC) is written with address X; the instruction at X is the next instruction to execute
PC The address of the assembly instruction in question
rA, rB, rC One of the 32-bit general-purpose registers
prs.rA General-purpose register rA in the previous register set
IMMn An n-bit immediate value, embedded in the instruction word
IMMED An immediate value
Xn The nth bit of X, where n = 0 is the LSB
Xn .. m Consecutive bits n through m of X
0xNNMM Hexadecimal notation
X : Y Bitwise concatenation

For example, (0x12 : 0x34) = 0x1234

σ(X) The value of X after being sign-extended to a full register-sized signed integer
X >> n The value X after being right-shifted n bit positions
X << n The value X after being left-shifted n bit positions
X & Y Bitwise logical AND
X | Y Bitwise logical OR
X ^ Y Bitwise logical XOR
~X Bitwise logical NOT (one’s complement)
Mem8[X] The byte located in data memory at byte address X
Mem16[X] The halfword located in data memory at byte address X
Mem32[X] The word located in data memory at byte address X
label An address label specified in the assembly file
(signed) rX The value of rX treated as a signed number
(unsigned) rX The value of rX treated as an unsigned number
Note: All register operations apply to the current register set, except as noted.

The following exceptions are not listed for each instruction because they can occur on any instruction fetch:

  • Supervisor-only instruction address
  • Fast TLB miss (instruction)
  • Double TLB miss (instruction)
  • TLB permission violation (execute)
  • MPU region violation (instruction)

    For information about these and all Nios II exceptions, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

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