Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.3.1. Overview

The Nios II/s core:
  • Has an instruction cache, but no data cache
  • Can access up to 2 GB of external address space
  • Supports optional tightly-coupled memory for instructions
  • Employs a 5-stage pipeline
  • Performs static branch prediction
  • Provides hardware multiply, divide, and shift options to improve arithmetic performance
  • Supports the addition of custom instructions
  • Supports the JTAG debug module
  • Supports optional JTAG debug module enhancements, including hardware breakpoints and real-time trace

The following sections discuss the noteworthy details of the Nios II/s core implementation. This document does not discuss low-level design issues or implementation details that do not affect Nios® II hardware or software designers.

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