Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

4.7.1. ECC

ECC is only available for the Nios® II/f core and provides ECC support for Nios® II internal RAM blocks, such as instruction cache, MMU TLB, and register file. The SECDED ECC algorithm is based on Hamming codes, which detect 1 or 2 bit errors and corrects 1 bit errors. If the Nios® II processor does not attempt to correct any errors and only detects them, the ECC algorithm can detect 3 bit errors.

Refer to "ECC" section in the Nios® II Core Implementation Details chapter for more information about ECC support in the Nios® II/f core.