Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

4.5.2. MPU

When Include MPU on the MMU and MPU Settings tab is on, the MPU settings on the MMU and MPU Settings tab provide the following options for the MPU in the Nios II/f core.

  • Use Limit for region range—Controls whether the amount of memory in the region is defined by size or by upper address limit. When on, the amount of memory is based on the given upper address limit. When off, the amount of memory is based on the given size.
  • Number of data regions—Specifies the number of data regions to allocate. Allowed values range from 2 to 32.
  • Minimum data region size—Specifies the minimum data region size. Allowed values range from 256 bytes to 1 MB and must be a power of two.
  • Number of instruction regions—Specifies the number of instruction regions to allocate. Allowed values range from 2 to 32.
  • Minimum instruction region size—Specifies the minimum instruction region size. Allowed values range from 256 bytes to 1 MB and must be a power of two.
Note: The maximum region size is the size of the Nios II instruction and data addresses automatically determined when the Nios® II system is generated in Platform Designer. Maximum region size is based on the address range of slaves connected to the Nios II instruction and data masters.

For information about the MPU, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

For specifics on the Nios II/f core, refer to the Nios II Core Implementation Details chapter of the Nios® II Processor Reference Handbook.

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