Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

8.5.88. sth / sthio

Instruction store halfword to memory or I/O peripheral
Operation

Mem16[rA + σ(IMM16)] ←  rB15..0

Assembler Syntax

sth rB, byte_offset(rA)

sthio rB, byte_offset(rA)

Example

sth r6, 100(r5)

Description

Computes the effective byte address specified by the sum of rA and the instruction's signed 16-bit immediate value. Stores the low halfword of rB to the memory location specified by the effective byte address. The effective byte address must be halfword aligned. If the byte address is not a multiple of 2, the operation is undefined.

Usage

In processors with a data cache, this instruction may not generate an Avalon® -MM data transfer immediately. Use the sthio instruction for peripheral I/O. In processors with a data cache, sthio bypasses the cache and is guaranteed to generate an Avalon® -MM data transfer. In processors without a data cache, sthio acts like sth.

Exceptions

Supervisor-only data address

Misaligned data address

TLB permission violation (write)

Fast TLB miss (data)

Double TLB miss (data)

MPU region violation (data)

Instruction Type

I

Instruction Fields

A = Register index of operand rA

B = Register index of operand rB

IMM16 = 16-bit signed immediate value

Table 107.  sth
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x0d
Table 108.  sthio
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A B IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x2d

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