Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.14.3. The MT Flag

The MT flag determines the default memory type of an MPU data region. . The MT flag only applies to data regions. For instruction regions, the MT bit must be written with 0 for instruction regions and is always read as 0.

When data cacheability is enabled on a data region, a data access to that region can be cached, if a data cache is present in the system. You can override the default cacheability and force an address to noncacheable with an ldwio or stwio instruction. The encoding of the MT field is setup to be backwards-compatible with the Nios® II Classic core MPU where bit 5 of MPUACC contains the cacheable bit (0 = non-cacheable, 1 = cacheable) and bit 6 is zero.
Instruction Bit 31 Bypass Data Cache MT Flag Value Data Access
ldwio/stwio don’t care don’t care non-cacheable
ldw/stw 1 don’t care non-cacheable
ldw/stw 0 0 or 2 non-cacheable
ldw/stw 0 1 cacheable
Note: The bit 31 cache bypass and peripheral region features are supported when the MPU is present. Refer to the Cache memory section for more information on cache bypass.

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