Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6.2.3.3. Peripheral Region

Nios® II cores optionally support a new peripheral region mechanism to indicate cacheability. The peripheral region cacheability mechanism allows a user at Platform Designer generation time to specify a region of address space that is treated as non-cacheable. The peripheral region is any integer power of 2 bytes from a minimum of 4096 bytes up to a maximum of 2 GBytes and must be located at a base address aligned to the size of the peripheral region. The peripheral region is available as long as an MMU is not present.

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