184.108.40.206. External Interrupt Controller Interface
The Nios® II processor does not depend on any particular implementation of an EIC. The degree of EIC configurability, and EIC configuration methods, are implementation-specific. This section discusses the EIC interface, and general features of EICs. For usage details, refer to the documentation for the specific EIC in your system.
When an IRQ is asserted, the EIC presents the following information to the Nios® II processor:
- The requested handler address (RHA)—Refer to the Requested Handler Address section of this chapter
- The requested interrupt level (RIL)—Refer to the Requested Interrupt Level section of this chapter
- The requested register set (RRS)—Refer to Requested Register Set section of this chapter
- Requested nonmaskable interrupt (RNMI) mode—Refer to the Requested NMI Mode section of this chapter
The Nios® II processor EIC interface connects to a single EIC, but an EIC can support a daisy-chained configuration. In a daisy-chained configuration, multiple EICs can monitor and prioritize interrupts. The EIC directly connected to the processor presents the processor with the highest-priority interrupt from all EICs in the daisy chain.
An EIC component can support an arbitrary level of daisy-chaining, potentially allowing the Nios® II processor to handle an arbitrary number of prioritized interrupts.
For a typical EIC implementation, refer to the Vectored Interrupt Controller chapter in the Embedded Peripherals IP User Guide.
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