126.96.36.199. Exception Flow with the EIC Interface
- RHA—The requested handler address for the interrupt handler assigned to the requested interrupt.
- RRS—The requested register set to be used when the interrupt handler executes. If shadow register sets are not implemented, RRS must always be 0.
- RIL—The requested interrupt level specifies the priority of the interrupt.
- RNMI—The requested NMI flag specifies whether to treat the interrupt as nonmaskable.
For further information about the RHA, RRS, RIL and RNMI, refer to “The Nios II/f Core” in the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.
When the EIC interface presents an interrupt to the Nios® II processor, the processor uses several criteria, as follows, to determine whether to take the interrupt:
- Nonmaskable interrupts—The processor takes any NMI as long as it is not processing a previous NMI.
- Maskable interrupts—The processor takes a maskable interrupt if maskable interrupts are enabled, and if the requested interrupt level is higher than that of the interrupt currently being processed (if any). However, if shadow register sets are implemented, the processor takes the interrupt only if the interrupt requests a register set different from the current register set, or if the register set interrupt enable flag (status.RSIE) is set.
Table 40. Conditions Required to Take External Interrupt RNMI == 1 RNMI == 0 status.NMI == 0 status.NMI == 1 status.PIE == 0 status.PIE == 1 RIL <= status.IL RIL > status.IL Processor Has Shadow Register Sets No Shadow Register Sets RRS == status.CRS RRS != status.CRS status.RSIE == 0 status.RSIE == 1 Yes No No No No 13 Yes Yes Yes
The Nios® II processor supports fast nested interrupts with shadow register sets, as described in the "Shadow Register Set" section of this chapter.
Keeping status.PIE set allows higher level interrupts to be taken immediate, without requiring the interrupt handler to set status.PIE to 1.
The processor disables maskable interrupts when taking an exception, just as it does without shadow register sets. An individual interrupt handler can re-enable interrupts by setting status.PIE to 1, if desired.
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