Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

4.2.3. Fast TLB Miss Exception Vector

The fast TLB miss exception vector is a special exception vector used exclusively by the MMU to handle TLB miss exceptions. Parameters in this section select the memory module where the fast TLB miss exception vector (exception address) resides, and the location of the fast TLB miss exception vector. The fast TLB miss exception vector cannot be configured until your system memory components are in place.

The Fast TLB Miss Exception vector memory list, which includes all memory modules mastered by the Nios® II processor, selects the exception vector memory module. In a typical system, select a low-latency memory module for the exception code.

Note: Platform Designer provides an Absolute option, which allows you to specify an absolute address in Fast TLB Miss Exception vector offset. Use an absolute address when the memory storing the exception handler is located outside of the processor system and subsystems of the processor system.

Fast TLB Miss Exception vector offset specifies the location of the exception vector relative to the memory module’s base address. Platform Designer calculates the physical address of the exception vector when you modify the memory module, the offset, or the memory module’s base address. In Platform Designer, Fast TLB Miss Exception vector displays the readonly, calculated address. The address is always a physical address, even when an MMU is present.

Note: The Nios® II MMU is optional and mutually exclusive from the Nios® II MPU. Nios® II systems can include either an MMU or MPU, but cannot include both an MMU and MPU in the same design.

For information about the Nios® II MMU, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

To function correctly with the MMU, the base physical address of all exception vectors (reset, general exception, break, and fast TLB miss) must point to low physical memory so that hardware can correctly map their virtual addresses into the kernel partition. This restriction is enforced by the Nios® II Processor parameter editor.