188.8.131.52. Data Master Port
- Read data from memory or a peripheral when the processor executes a load instruction
- Write data to memory or a peripheral when the processor executes a store instruction
Byte-enable signals on the master port specify which of the four byte-lane(s) to write during store operations. Load and store operations can complete in a single clock cycle when the data master port is connected to zero-wait-state memory.
The Nios II architecture supports on-chip cache memory for improving average data transfer performance when accessing slower memory. Refer to the "Cache Memory" section of this chapter for details.
The Nios II architecture supports tightly-coupled memory, which provides guaranteed low-latency access to on-chip memory. Refer to "Tightly-Coupled Memory" section of this chapter for details.
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