Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents Instruction and Data Master Ports

The instruction master port is a pipelined Avalon® Memory-Mapped ( Avalon® -MM) master port. The core also includes a data cache with a fixed 32-byte line size, making he data master port a pipelined Avalon® -MM master port.

The instruction and data master ports on the Nios II/f core are optional. A master port can be excluded, as long as the core includes at least one tightly-coupled memory to take the place of the missing master port.

Note: Although the Nios® II processor can operate entirely out of tightly-coupled memory without the need for Avalon® -MM instruction or data masters, software debug is not possible when either the Avalon® -MM instruction or data master is omitted.

Support for pipelined Avalon® -MM transfers minimizes the impact of synchronous memory with pipeline latency. The pipelined instruction and data master ports can issue successive read requests before prior requests complete.