Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

4.5.1. MMU

When Include MMU on the MMU and MPU Settings tab is on, the MMU settings on the MMU and MPU Settings tab provide the following options for the MMU in the Nios II/f core. Typically, you should not need to change any of these settings from their default values.

  • Process ID (PID) bits—Specifies the number of bits to use to represent the process identifier.
  • Optimize number of TLB entries based on device family—When on, specifies the optimal number of TLB entries to allocate based on the device family of the target hardware and disables TLB entries.
  • TLB entries—Specifies the number of entries in the translation lookaside buffer (TLB).
  • TLB Set-Associativity—Specifies the number of set-associativity ways in the TLB.
  • Micro DTLB entries—Specifies the number of entries in the micro data TLB.
  • Micro ITLB entries—Specifies the number of entries in the micro instruction TLB.

For information about the MMU, refer to the Programming Model chapter of the Nios® II Processor Reference Handbook.

For specifics on the Nios II/f core, refer to the Nios II Core Implementation Details chapter of the Nios® II Processor Reference Handbook.

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