Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

5.4.1. Overview

The Nios II/e core:
  • Executes at most one instruction per six clock cycles
  • Full 32-bit addressing
  • Can access up to 4 GB of external address space
  • Supports the addition of custom instructions
  • Supports the JTAG debug module
  • Does not provide hardware support for potential unimplemented instructions
  • Has no instruction cache or data cache
  • Does not perform branch prediction

The following sections discuss the noteworthy details of the Nios II/e core implementation. This document does not discuss low-level design issues, or implementation details that do not affect Nios® II hardware or software designers.