Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

8.5.46. flushda

Instruction flush data cache address

Flushes the data cache line currently caching address rA + σ(IMM16)

Assembler Syntax

flushda IMM16(rA)


flushda -100(r6)


If the Nios® II processor implements a direct mapped data cache, flushda writes the data cache line that is mapped to the specified address back to memory if the line is dirty, and then clears the data cache line. Unlike flushd, flushda writes the dirty data back to memory only when the addressed data is currently in the cache. This process comprises the following steps:

  • Compute the effective address specified by the sum of rA and the signed 16-bit immediate value.
  • Identify the data cache line associated with the computed effective address. Each data cache effective address comprises a tag field and a line field. When identifying the line, flushda uses both the tag field and the line field.
  • Compare the cache line tag with the effective address to determine if the addressed data is currently cached. If the tag fields do not match, the effective address is not currently cached, so the instruction does nothing.
  • If the data cache line is dirty and the tag fields match, write the dirty cache line back to memory. A cache line is dirty when one or more words of the cache line have been modified by the processor, but are not yet written to memory.
  • Clear the valid bit for the line.

    If the Nios® II processor core does not have a data cache, the flushda instruction performs no operation.


Use flushda to write dirty lines back to memory only if the addressed memory location is currently in the cache, and then flush the cache line. By contrast, refer to “flushd flush data cache line”, “initd initialize data cache line”, and “initda initialize data cache address” for other cache-clearing options.

For more information on the Nios II data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook.


Supervisor-only data address

Fast TLB miss (data)

Double TLB miss (data)

MPU region violation (data)

Instruction Type


Instruction Fields

A = Register index of operand rA

IMM16 = 16-bit signed immediate value

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A 0 IMM16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMM16 0x1b