Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.7.8. Misaligned Data Address

The Nios® II processor can check for misaligned data addresses of load and store instructions and generate an exception when a misaligned data address is encountered. When your system contains an MMU or MPU, misaligned data address checking is always on. When no MMU or MPU is present, you have the option to have the processor check for misaligned data addresses.

For information about controlling this option, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.

A data address is considered misaligned if the byte address is not a multiple of the width of the load or store instruction data width (four bytes for word, two bytes for half-word). Byte load and store instructions are always aligned so never take a misaligned address exception.

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