184.108.40.206. Misaligned Data Address
For information about controlling this option, refer to the Instantiating the Nios® II Processor chapter of the Nios® II Processor Reference Handbook.
A data address is considered misaligned if the byte address is not a multiple of the width of the load or store instruction data width (four bytes for word, two bytes for half-word). Byte load and store instructions are always aligned so never take a misaligned address exception.
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