Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.6.3.5. Data Cache Tag RAM

  1. Use a LOAD instruction from a data address to get the line in the cache. The line should be clean.
  2. Use a WRCTL instruction to set ECCINJ.DCTAG to INJS or INJD.
  3. Use a STORE instruction from a data address mapped to that line. The STORE instruction should hit in the data cache and write the tag RAM to set the dirty bit.
  4. The ECC error is injected when the tag RAM is written.
  5. Use a RDCTL instruction to ensure the value of ECCINJ.DCTAG is NOINJ. Before the RDCTL, use a FLUSHP instruction to avoid the RAW hazard on ECCINJ.
  6. Do another LOAD or STORE instruction to the same line.
  7. The ECC error should be triggered on this second LOAD/STORE instruction.

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