Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

5.2.9. Exception Handling

The Nios II/f core supports the following exception types:
  • Hardware interrupts
  • Software trap
  • Illegal instruction
  • Unimplemented instruction
  • Supervisor-only instruction (MMU or MPU only)
  • Supervisor-only instruction address (MMU or MPU only)
  • Supervisor-only data address (MMU or MPU only)
  • Misaligned data address
  • Misaligned destination address
  • Division error
  • Error-correcting code (ECC)
  • Fast translation lookaside buffer (TLB) miss (MMU only)
  • Double TLB miss (MMU only)
  • TLB permission violation (MMU only)
  • MPU region violation (MPU only)

Did you find the information on this page useful?

Characters remaining:

Feedback Message