Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents Returning From Interrupt and Instruction-Related Exceptions

The eret instruction is used to resume execution at the pre-exception address.

You must ensure that when an exception handler modifies registers, they are restored when it returns. This can be taken care of in either of the following ways:

  • In the case of ISRs, if the EIC interface and shadow register sets are implemented, and the ISR has a dedicated register set, no software action is required. The Nios® II processor returns to the previous register set when it executes eret, which restores the register contents.
  • For details, refer to the "Nested Exceptions with an External Interrupt Controller" section of this chapter.
  • In the case of noninterrupt exceptions, for ISRs in a system with the internal interrupt controller, and for ISRs without a dedicated shadow register set, the exception handler must save registers on entry and restore them on exit. Saving the register contents on the stack is a typical, re-entrant implementation.
Note: It is not necessary to save and restore the exception temporary (et or r24) register.

When executing the eret instruction, the processor performs the following tasks:

  1. Restores the previous contents of status as follows:
    • If status.CRS is 0, copies estatus to status
    • If status.CRS is nonzero, copies sstatus to status
  2. Transfers program execution to the address in the ea register (r29) in the register set specified by the original value of status.CRS.
Note: The eret instruction can cause the processor to exit NMI mode. However, it cannot make the processor enter NMI mode. In other words, if status.NMI is 0 and estatus.NMI (or sstatus.NMI) is 1, after an eret, status.NMI is still 0. This restriction prevents the processor from accidentally entering NMI mode.
Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software, including ISRs, is built with the version of the GCC compiler included in Nios II EDS version 9.0 or later. Earlier versions have an implementation of the eret instruction that is incompatible with shadow register sets.