Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

4.3.3. Data Cache

The Data Cache parameters provide the following options for the Nios® II/f core:

  • Size—Specifies the size of the data cache. Valid sizes are from 512 bytes to 64 KBytes, or None. Depending on the value specified for Data cache, the following options are available:
  • Victim buffer implementation—Specifies whether to use RAM or registers. The data cache victim buffer temporarily holds a dirty cache line while the data is written back to external memory.
  • Add burstcount signal to data_master—The Nios® II processor can fill its data cache lines using burst transfers. Usually you enable bursts on the processor's data bus when processor data is stored in DRAM, and disable bursts when processor data is stored in SRAM.

    Bursting to DRAM typically improves memory bandwidth but might consume additional FPGA resources. Be aware that when bursts are enabled, accesses to slaves might go through additional hardware (called burst adapters) which might decrease your fMAX.

    The burst length is always 8 for a 32-byte line size. Data cache bursts are always aligned on the cache line boundary. For example, with a 32-byte Nios® II data cache line, a cache miss to the address 8 results in a burst with the following address sequence: 0, 4, 8, 12, 16, 20, 24 and 28.

  • Use most-significant address bit in processor to bypass data cache—This option is enabled by default, the data master interfaces only support up to 31-bit byte address. Disable this option to support full 32-bit byte address

Although the Nios® II processor can operate entirely out of tightly-coupled memory without the need for Avalon® -MM instruction or data masters, software debug is not possible when either the Avalon® -MM instruction or data master is omitted.

Note: By default this feature is turned on for backwards compatibility with the Nios® II Classic core.