Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

5.3.6. Instruction Performance

All instructions take one or more cycles to execute. Some instructions have other penalties associated with their execution. Instructions that flush the pipeline cause up to three instructions after them to be cancelled. This creates a three-cycle penalty and an execution time of four cycles. Instructions that require an Avalon® -MM transfer are stalled until the transfer completes.
Table 71.  Instruction Execution Performance for Nios II/s Core
Instruction Cycles Penalties
Normal ALU instructions (e.g., add, cmplt) 1  
Combinatorial custom instructions 1  
Multicycle custom instructions > 1  
Branch (correctly predicted taken) 2  
Branch (correctly predicted not taken) 1  
Branch (mispredicted) 4 Pipeline flush
trap, break, eret, bret, flushp, wrctl, unimplemented 4 Pipeline flush
jmp, jmpi, ret, call, callr 4 Pipeline flush
rdctl 1  
load, store > 1  
flushi, initi 4  
Shift/rotate (with hardware multiply using embedded multipliers) 3  
Shift/rotate (with hardware multiply using LE-based multipliers) 4  
Shift/rotate (without hardware multiply present) 1 to 32  
All other instructions 1