Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Document Table of Contents

2. Processor Architecture

This chapter describes the hardware structure of the Nios® II processor, including a discussion of all the functional units of the Nios II architecture and the fundamentals of the Nios® II processor hardware implementation.

The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions. A Nios® II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture.

The Nios II architecture defines the following functional units:

  • Register file
  • Arithmetic logic unit (ALU)
  • Interface to custom instruction logic
  • Exception controller
  • Internal or external interrupt controller
  • Instruction bus
  • Data bus
  • Memory management unit (MMU)
  • Memory protection unit (MPU)
  • Instruction and data cache memories
  • Tightly-coupled memory interfaces for instructions and data
  • JTAG debug module
Figure 2.  Nios® II Processor Core Block Diagram