Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.7.13.3. Masking Interrupts with the Internal Interrupt Controller

The ienable register controls the handling of internal hardware interrupts. Each bit of the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A value of one in bit n means that the corresponding irqn interrupt is enabled; a bit value of zero means that the corresponding interrupt is disabled.

Refer to the "Exception Processing" section of this chapter for more information.

An ISR can adjust ienable so that IRQs of equal or lower priority are disabled. Refer to the "Handling Nested Exceptions" section of this chapter for more information.

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