Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.4.2.13. The mpubase Register

The mpubase register works in conjunction with the mpuacc register to set and retrieve MPU region information and is only available in systems with an MPU.

Table 27.  mpubase Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE6 0 INDEX5 D
Table 28.  mpubase Control Register Field Descriptions
Field Description Access Reset Available
BASE BASE is the base memory address of the region identified by the INDEX and D fields. Read/Write 0 Only with MPU
INDEX INDEX is the region index number. Read/Write 0 Only with MPU
D D is the region access bit. When D =1, INDEX refers to a data region. When D = 0, INDEX refers to an instruction region. Read/Write 0 Only with MPU

The BASE field specifies the base address of an MPU region. The 24-bit BASE field corresponds to bits 8 through 31 of the base address, making the base address always a multiple of 256 bytes. If the minimum region size (set in Platform Designer at generation time) is larger than 256 bytes, unused low-order bits of the BASE field must be written as zero and are read as zero. For example, if the minimum region size is 1024 bytes, the two least-significant bits of the BASE field (bits 8 through 9 of the mpubase register) must be zero. Similarly, if the Nios II address space is less than 31 bits, unused high-order bits must also be written as zero and are read as zero.

The INDEX and D fields specify the region information to access when an MPU region read or write operation is performed. The D field specifies whether the region is a data region or an instruction region. The INDEX field specifies which of the 32 data or instruction regions to access. If there are fewer than 32 instruction or 32 data regions, unused high-order bits must be written as zero and are read as zero.

Refer to the MPU Region Read and Write Operations section for more information on MPU region read and write operations.

5 This field size is variable. Unused upper bits must be written as zero.
6 This field size is variable. Unused upper bits and unused lower bits must be written as zero.

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