Nios® II Processor Reference Guide

ID 683836
Date 8/28/2023
Public
Document Table of Contents
Give Feedback

4.3. Caches and Memory Interfaces Tab

The Caches and Memory Interfaces tab allows you to configure the cache and tightly-coupled memory usage for the instruction and data master ports.
Figure 8.  Nios® II Platform Designer Caches and Memory Interfaces Tab