Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

3.8. Memory and Peripheral Access

Nios II addresses are 32 bits, allowing access up to a 4-gigabyte address space. The MMU supports the full 32-bit physical address. Bit 31 bypass is optional, you can access full 32-bit addressing without the MMU.

For details, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.

Peripherals, data memory, and program memory are mapped into the same address space. The locations of memory and peripherals within the address space are determined at system generation time. Reading or writing to an address that does not map to a memory or peripheral produces an undefined result.

The processor’s data bus is 32 bits wide. Instructions are available to read and write byte, half-word (16-bit), or word (32-bit) data.

The Nios II architecture uses little-endian byte ordering. For data wider than 8 bits stored in memory, the more-significant bits are located in higher addresses.

The Nios II architecture supports register and immediate addressing.

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