6. Nios® II Processor Versions
Improvements to the Nios® II processor might affect:
- Features of the Nios® II architecture—An example of an architecture revision is adding instructions to support floating-point arithmetic.
- Implementation of a specific Nios® II core—An example of a core revision is increasing the maximum possible size of the data cache memory for the Nios® II/f core.
- Features of the JTAG debug module—An example of a JTAG debug module revision is adding an additional trigger input to the JTAG debug module, allowing it to halt processor execution on a new type of trigger event.
Intel FPGA implements Nios® II revisions such that code written for an existing Nios® II core also works on future revisions of the same core.
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