Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.4. Reset and Debug Signals

The table below describes the reset and debug signals that the Nios® II processor core supports.
Table 2.   Nios® II Processor Debug and Reset Signals
Signal Name Type Purpose
reset Reset This is a global hardware reset signal that forces the processor core to reset immediately.
cpu_resetrequest Reset This is an optional, local reset signal that causes the processor to reset without affecting other components in the Nios® II system. The processor finishes executing any instructions in the pipeline, and then enters the reset state. This process can take several clock cycles, so be sure to continue asserting the cpu_resetrequest signal until the processor core asserts a cpu_resettaken signal.

The processor core asserts a cpu_resettaken signal for 1 cycle when the reset is complete and then periodically if cpu_resetrequest remains asserted. The processor remains in the reset state for as long as cpu_resetrequest is asserted. While the processor is in the reset state, it periodically reads from the reset address. It discards the result of the read, and remains in the reset state.

The processor does not respond to cpu_resetrequest when the processor is under the control of the JTAG debug module, that is, when the processor is paused. The processor responds to the cpu_resetrequest signal if the signal is asserted when the JTAG debug module relinquishes control, both momentarily during each single step as well as when you resume execution.

debug_reset_request Reset This reset output signal appears when the JTAG Debug module is enabled. This signal is triggered by the JTAG debugger or nios2-download -r command. This signal must be connected to the reset input signal of the Nios® II processor which allows the JTAG debugger to reset the processor. This signal can be connected to the reset input signal of other components when needed.
debugreq Debug This is an optional signal that temporarily suspends the processor for debugging purposes. When you assert the signal, the processor pauses in the same manner as when a breakpoint is encountered, transfers execution to the routine located at the break address, and asserts a debugack signal. Asserting the debugreq signal when the processor is already paused has no effect.
reset_req Reset This optional signal prevents the memory corruption by performing a reset handshake before the processor resets.

For more information about adding reset signals and debug signals to the Nios® II processor, refer to Advanced Features Tab and JTAG Debug Module Tab in the Instantiating the Nios® II Processor chapter respectively.

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