Nios® II Processor Reference Guide

ID 683836
Date 10/22/2020
Public
Document Table of Contents

2.6.2.3.2. The Bit-31 Cache Bypass Method

The bit-31 cache bypass method on the data master port uses bit 31 of the address as a tag that indicates whether the processor should transfer data to/from cache, or bypass it. This is a convenience for software, which might need to cache certain addresses and bypass others. Software can pass addresses as parameters between functions, without having to specify any further information about whether the addressed data is cached or not.

To determine which cores implement which cache bypass methods, refer to the Nios II Core Implementation Details chapter of the Nios® II Processor Reference Handbook.

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